1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device and, more particularly, to a method for manufacturing a nonvolatile memory device.
2. Description of the Related Art
The nonvolatile memory device is widely used in a computer or a memory card because information stored in a memory cell thereof is not erased even when power supply is turned off. A cell transistor of the nonvolatile memory device has a stacked gate structure in which a floating gate, an insulating layer, and a control gate electrode are sequentially formed on a tunnel oxide layer. In the stacked gate structures the floating gate stores electric charge and the control gate electrode serves as a wordline. However, a MOS transistor used for a peripheral circuit of the nonvolatile memory device includes a single gate electrode formed on a predetermined region of the gate insulating layer. The single gate electrode of the MOS transistor makes it difficult to form the gate pattern of both cell transistors through the same process.
A method for forming the single gate electrode of the MOS transistor formed on the peripheral circuit region and the gate pattern of the cell transistor formed on the cell array region using the same process is disclosed in Japanese Pat. No. 59,074,677A ("'677A patent"). According to the '677A patent, the gate pattern of the MOS transistor formed on the peripheral circuit region has the same stacked gate structure as that of the cell transistor. The '677A patent describes the MOS transistor as comprising first and second conductive layers and a dielectric layer interposed therebetween. The first and second conductive layers of the MOS transistor are electrically connected through a first contact hole passing through a predetermined region of the dielectric layer. Also, the second conductive layer is electrically connected to a metal interconnection through a second contact hole passing through a predetermined region of the interdielectric layer formed on the second conductive layer. The second conductive layer forms the gate pattern of the MOS transistor. The first conductive layer then is connected to a metal interconnection through the first and the second contact holes. As a result, the second conductive layer is interposed between the gate electrode of the MOS transistor forming the peripheral circuit and the metal interconnection. Thus, contact resistance between the first conductive layer and the second conductive layer deteriorates the propagation speed of an electric signal applied to the gate electrode of the MOS transistor. Also, according to the '677A patent, the second conductive layer is stacked on the first conductive layer such that forming a resistor using only the first conductive layer is difficult. The first conductive layer is generally formed of a polysilicon layer. When the resistor is formed of the first conductive layer, it is easy to control the resistance value of the resistor. Thus, it is difficult to form a resistor having a desired resistance value using the methodology disclosed in the '677A patent.